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White Electronic Designs
2x32Mx16bit DDR SDRAM
FEATURES
Double-data-rate architecture; two data transfers per clock cycle Data rate = 200, 266, 333, 400 Mbs Package: * 66pin TSOP II package 2.5V 0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs(CK and CK#) DLL aligns DQ and DQS transition with CK MRS cycle with address key programs * Read latency : 2, 2.5 , 3 (Clock) * Burst length (2, 4, or 8) * Burst type (sequential & interleave) Auto & Self refresh Modes RoHS Compliant Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
W3E232M16S-XSTX
PRELIMINARY*
Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, and Industrial Temperature Ranges Organized as 2X32M x 16
* This product is under development, is not qualified +and is subject to change without notice.
OPERATING FREQUENCIES
DDR400 Speed @CL2 Speed @CL2.5 Speed @CL3
* CL = CAS Latency
DDR333 133MHz 166MHz --
DDR266 133MHz 133MHz --
DDR200 100MHz 133MHz --
-- 166MHz 200MHz
FUNCTIONAL BLOCK DIAGRAM
CK, CK#, CAS, LDM, UDM RAS#, WE#, UDQS, LDQS CS0#, CKE0
32Mx16
32Mx16
CS1#, CKE1
A0-A12, BA0, BA1 I/O0 ~ I/O15
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PIN CONFIGURATION
W3E232M16S-XSTX
PRELIMINARY*
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 NC VCCQ LDQS NC VCC DNU LDM WE# CAS# RAS# CS0# CS1# BA0 BA1 AP/A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
66 65 64 63 62 61 60 59 58
VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 NC VSSQ UDQS DNU VREF VSS UDM CK# CK CKE0 CKE1 A12 A11 A9 A8 A7 A6 A5 A4 VSS
66Pin TSOPII (400mil x 875mil) (0.65mm Pin Pitch)
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
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PACKAGE DIMENSIONS
W3E232M16S-XSTX
PRELIMINARY*
0.483" MIN 0.487" MAX #1 #66
0.105"/+0.005"/-0.00"
0.880"/0.005"
0.026"/0.003"
0.012"/0.003"
#33
#34
Top View
Side View
Bottom View
0.483" MIN 0.487" MAX
0.105"/+0.005"/-0.00"
TSOP TSOP
MAIN PCB
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GENERAL DESCRIPTION
The 2x32Mx16 (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 2 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. The 2x32Mx16 DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 2x32Mx16 DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte. The 2x32Mx16 DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective
W3E232M16S-XSTX
PRELIMINARY*
bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with the Jedec Standard for SSTL_2. All full drive options outputs are SSTL_2, Class II compatible.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VCC and VCCQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VCCQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VCC is applied. After CKE passes through VIH, it will transition to an SSTL_2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during powerup is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should
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be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cy cles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating pa ram e ters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation.
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BURST LENGTH
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Fig ure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four (where Ai is the most significant column address for a given configuration); and by A3-Ai when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
REGISTER DEFINITION MODE REGISTER
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 3. The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. (Except for bit A8 which is self clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
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OPERATING MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
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PRELIMINARY*
controller must wait the specified time before initiating any sub se quent operation. Violating either of these requirements could result in unspecified operation.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to be SSTL2, Class II. The DDR SDRAM supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during powerup initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE high must occur before a READ command can be issued.device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL.The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC. These functions are controlled via the bits shown
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED -200 -266 -333 -400 CAS LATENCY = 2 75 100 - CAS LATENCY = 2.5 100 133 166 166 CAS LATENCY = 3 166 200
COMMANDS
The Truth Table provides a quick reference of available commands. This is followed by a written description of each command.
in Figure 5. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the
DESELECT
The DESELECT function (CS# High) prevents new commands from being executed by the DDR SDRAM. The SDRAM is effectively deselected. Operations already in progress are not affected.
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NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to the selected DDR SDRAM (CS# is LOW while RAS#, CAS#, and WE# are high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
W3E232M16S-XSTX
PRELIMINARY*
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-9 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses
FIGURE 3 - MODE REGISTER DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
14
0*
13
0*
12 11 10 9
87
6
5
4
3
BT
2
1
0
Mode Register (Mx)
Operating Mode
CAS Latency
Burst Length
* M14 and M13 (BA0 and BA1 must be "0, 0" to select the base mode register (vs. the extended mode register).
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11 M3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved M3 = 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses
M3 0 1
Burst Type Sequential Interleaved
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the
M6 M5 M4 0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11
CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved
M12 0 0 -
M11 0 0 -
M10 0 0 -
M9 0 0 -
M8 0 1 -
M7 0 0 -
M6-M0 Valid Valid -
Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved
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TABLE 1 - BURST DEFINITION
Burst Length Starting Column Address A0 2 0 1 A1 0 4 0 1 1 A2 0 0 0 8 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
DQS DQ
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PRELIMINARY*
FIGURE 4 - CAS LATENCY
T0 CLK# CLK T1 T2 T2n T3 T3n
Order of Accesses Within a Burst Type = Sequential Type = Interleaved
0-1 1-0
0-1 1-0
COMMAND
READ
NOP CL = 2
NOP
NOP
DQS
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0
DQ
T0 CLK# CLK COMMAND READ
T1
T2
T2n
T3
T3n
NOP CL = 2.5
NOP
NOP
Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DATA TRANSITIONING DATA DON'T CARE
process of precharging.
NOTES: 1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column within the block. 2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column within the block. 3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting column within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. This "earliest valid stage" is determined as if an explicit precharge command was issued at the earliest possible time, without violating tRAS (MIN).The user must not issue another command to the same bank until the precharge time (tRP) is completed.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. The device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank.
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BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ burst was terminated from remains open.
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PRELIMINARY*
FIGURE 5 - EXTENDED MODE REGISTER DEFINITION
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
14 13 12 11 10 9 8
01 11
7
6
5
4
3
2
1
0
Operating Mode
DS DLL
Extended Mode Register (Ex)
AUTO REFRESH
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS-BEFORE-RAS (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All banks must be idle before an AUTO REFRESH command is issued. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care"
E12 E11 E10 E9 0 0 0 0 E8 0 E7 0 E6 0 E5 0 E4 0 E3 0 E2 0 E1, E0 Valid Operating Mode Reserved Reserved E0 0 1 E1 0 1 DLL Enable Disable Drive Strength Normal Reduced
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register) 2. The QFC# function is not supported.
TRUTH TABLE - COMMANDS (NOTE 1)
NAME (FUNCTION) DESELECT (NOP) (9) NO OPERATION (NOP) (9) ACTIVE (Select bank and activate row) ( 3) READ (Select bank and column, and start READ burst) (4) WRITE (Select bank and column, and start WRITE burst) (4) BURST TERMINATE (8) PRECHARGE (Deactivate row in bank or banks) ( 5) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) LOAD MODE REGISTER (2)
NOTES: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0). 3. A0-12 provide row address, and BA0, BA1 provide bank address. 4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide bank address. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care."
CS# H L L L L L L L L
6.
RAS# X H L H H H L L L
CAS# X H H L L H H L L
WE# X H H H L L L H L
ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data.
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TRUTH TABLE - DM OPERATION
NAME (FUNCTION) WRITE ENABLE (10) WRITE INHIBIT (10) DM L H DQs Valid X
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during an AUTO REFRESH command. Each DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125s (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 7.8125s (70.3s). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (High) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later.
The procedure for exiting self refresh requires a sequence of commands. First, CK and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR, because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for tXSNR time, then a DLL Reset and NOPs for 200 additional clock cycles before applying any other command.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (A DLL reset and 200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. VREF voltage is also required for the full duration of SELF REFRESH.
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on VCC, VCCQ Supply relative to Vss Voltage on I/O pins relative to Vss Operating Temperature TA (Mil) Operating Temperature TA (Ind) Storage Temperature, Plastic -1 to 3.6
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Unit V V C C C -0.5V to VCCQ +0.5V -55 to +125 -40 to +85 -55 to +125
NOTE:Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (NOTE 13)
Parameter
Input Capacitance: CK/CK# Addresses, BA0-1 Input Capacitance Input Capacitance: All other input-only pins Input/Output Capacitance: I/Os
Symbol
CI1 CA CI2 CIO
Max
6 8 6 10
Unit
pF pF pF pF
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)
VCC, VCCQ = +2.5V 0.2V; -55C TA +125C Symbol VCC VCCQ VCC VCCQ II IOZ IOH IOL IOHR IOLR VREF VTT Parameter/Condition Supply Voltage (36, 41) I/O Supply Voltage (36, 41, 44) Supply Voltage 400Mbs (36,40) I/O Supply Voltage 400Mbs (36, 41, 44) Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V) Output Leakage Current: I/Os are disabled; 0V VOUT VCCQ Output Levels: Full drive option (37, 39) High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) Output Levels: Reduced drive option (38, 39) High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) I/O Reference Voltage (6,44) I/O Termination Voltage (7, 44)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
Min 2.3 2.3 2.5 2.5 -4 -10 -12 12 -9 9 0.49 x VCCQ VREF - 0.04
Max 2.7 2.7 2.7 2.7 4 10 0.51 x VCCQ VREF + 0.04
Units V V V V A A mA mA mA mA V V
White Electronic Designs
AC INPUT OPERATING CONDITIONS
VCC, VCCQ = +2.5V 0.2V; -55C TA +125C Symbol VIH VIL Parameter/Condition Input High (Logic 1) Voltage Input Low (Logic 0) Voltage
W3E232M16S-XSTX
PRELIMINARY*
Min VREF +0.310 --
Max -- VREF -0.310
Units V V
IDD SPECIFICATIONS AND CONDITIONS
-40C TA +85C; VccQ = +2.6 0.1V, Vcc = +2.6V 0.1V Notes: 1-5, 10, 12, 14, 46 Parameter/Condition OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 4; tRC=tRC (MIN); tCK=tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK=tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; tCK=tCK; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK=tCK (MIN); CKE = (LOW) ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN) DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH BURST CURRENT: SELF REFRESH CURRENT; CKE 0.2V tREFC = tRFC(MIN) tREFC = 7.8us Standard Symbol IDD0 Max DDR400 310 Units mA Notes 22, 47
IDD1
370
mA
22, 47
IDD2P IDD2F
10 110
mA mA
23, 32, 49 50
IDD3P IDD3N
90 120
mA mA
23, 32, 49 22
IDD4R
380
mA
22, 47
IDD4W
380
mA
22
IDD5 IDD5A IDD6 IDD7
690 22 10 900
mA mA mA mA
49 27, 47 11 22, 48
OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed: tCK=tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
IDD SPECIFICATIONS AND CONDITIONS
W3E232M16S-XSTX
PRELIMINARY*
-40C TA +85C; VccQ = +2.6 0.1V, Vcc = +2.6V 0.1V Notes: 1-5, 10, 12, 14, 46 Parameter/Condition OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 4; tRC=tRC (MIN); tCK=tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK=tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; tCK=tCK; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK=tCK (MIN); CKE = (LOW) ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN) DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC(MIN) AUTO REFRESH BURST CURRENT: SELF REFRESH CURRENT; CKE 0.2V tREFC = 7.8us Standard Symbol IDD0 Max DDR333 260 DDR266 260 DDR200 230 Units mA Notes 22, 47, 53 22, 47, 53 23, 32, 49 50, 54
IDD1
320
320
290
mA
IDD2P IDD2F
10 90
10 90
10 85
mA mA
IDD3P IDD3N
70 100
70 100
60 90
mA mA
23, 32, 49, 54 22, 54
IDD4R
330
330
290
mA
22, 47, 53 22, 53
IDD4W
350
310
270
mA
IDD5 IDD5A IDD6 IDD7
580 20 10 810
580 20 10 800
560 20 10 700
mA mA mA mA
49, 54 27, 47, 54 11, 54 22, 48, 53
OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed: tCK=tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 13 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS DDR400
-40C TA +85C; VCCQ = +2.5V 0.2V, VCC = +2.6V 0.1V Notes: 1-5, 14-17. 33 AC Characteristics Parameter
Access window of DQs from CK/CK# CK high-level width CK low-level width CL = 3 Clock cycle time CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access WRITE command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (slew rate 0.5V/ns) Address and control setup time (slew rate 0.5V/ns) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time
t
DDR400 Symbol
tAC tCH tCL tCK (3) tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ IHF ISF -0.7 0.60 0.60 2.2 10 tHP-tQHS 0.50 40 15 55 70 15 15 0.9 0.4 10 0.25 0 0.4 15 0.6 1.1 0.6 70,000 0.72 0.2 0.2 tCH,tCL +0.70
Min
-0.70 0.45 0.45 5 7.5 0.40 0.40 1.75 -0.60 0.35 0.35
Max
+0.70 0.55 0.55 7.5 13 -
Unit
ns tCK tCK ns ns ns ns ns ns
Notes
30 30 51 45, 51 45, 51 26, 51 26, 51 31
+0.60
ns tCK tCK
0.40 1.28
ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK ns tCK ns tCK ns
25, 26
34 18, 42 18, 42 14 14
t
tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR
25, 26
35
49
43 43
20, 21 19
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 14 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS DDR400
-40C TA +85C; VCCQ = +2.5V 0.2V, VCC = +2.6V 0.1V Notes: 1-5, 14-17. 33 AC Characteristics Parameter
Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Internal WRITE to READ command delay Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
DDR400 Symbol
tWTR N/A tREFC tREFI tVTD tXSNR tXSRD 0 70 200
Min
2 tQH - tDQSQ
Max
Unit
tCK ns
Notes
25 23 23
70.3 7.8
s s ns ns tCK
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 15 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS
-40C TA +85C; VCCQ = +2.5V 0.2V, VCC = +2.6V 0.1V Notes: 1-5, 14-17. 33 AC Characteristics Parameter
Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access WRITE command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time
t
DDR333 CL 2.5 DDR266 CL 2 Symbol
tAC tCH tCL CL = 2.5 CL = 2 tCK (3) tCK (2.5) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ IHF ISF IHs ISs -0.7 0.75 0.75 0.8 0.8 2.2 12 tHP-tQHS 0.55 40 15 60 72 15 15 0.9 0.4 12 0.25 0 1.1 0.6 70,000 0.75 0.2 0.2 tCH,tCL +0.7
DDR266 CL 2.5 DDR200 CL 2 Min
-0.70 0.45 0.45 7.5 10 0.5 0.5 1.75
Unit
ns tCK tCK ns ns ns ns ns
Notes
Min
-0.70 0.45 0.45 7.5 10 0.45 0.45 1.75 -0.6 0.35 0.35
Max
+0.70 0.55 0.55 13 13
Max
+0.70 0.55 0.55 13 13 30 30 51 45, 51 26, 51 26, 51 31
+0.6
-0.75 0.35 0.35
+0.75
ns tCK tCK
0.4 1.25 0.75 0.2 0.2 tCH,tCL
0.5 1.25
ns tCK tCK tCK ns
25, 26
34 18, 42 18, 42 14 14
+0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 40 20 65 75 20 20 0.9 0.4 15 0.25 0 1.1 0.6 120,000
ns ns ns ns
t
t
t
tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES
ns ns ns ns ns ns ns ns ns ns tCK tCK ns tCK ns 20, 21 43 43 49 35 25, 26
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 16 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS
-40C TA +85C; VCCQ = +2.5V 0.2V, VCC = +2.6V 0.1V Notes: 1-5, 14-17. 33 AC Characteristics Parameter
DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval (industrial) Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
DDR333 Symbol
tWPST tWR tWTR N/A tREFC tREFI tVTD tXSNR tXSRD 0 75 200
DDR266 Min
0.4 15 1
Min
0.4 15 1
Max
0.6
Max
0.6
Unit
Notes
19
s tQH - tDQSQ 70.3 7.8 ns s ns ns tCK
23
tQH - tDQSQ 70.3 7.8 0 75 200
25 23
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 17 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
NOTES: 1. All voltages referenced to VSS. 2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load:
VTT
W3E232M16S-XSTX
PRELIMINARY*
15.
16.
50 Output (VOUT) Reference Point 30pF
17. 18.
4.
5.
6.
7.
8. 9. 10. 11. 12. 13. 14.
AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed 2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. VID is the magnitude of the difference between the input level on CK and the input level on CK#. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of the same. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open. Enables on-chip refresh and address counters. ICC specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. This parameter is not tested but guaranteed by design. tA = 25C, F= 1 MHz For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per
19.
20. 21.
22.
23.
24. 25.
each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK# and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including SELF REFRESH mode, VREF must be powered within specified range. Exception: during the period before VREF stabilizes, CKE 0.3 x VCCQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). The intent of the Don't Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIHDC(MIN) then it must not transition low (below VIHDC) prior to tDQSH(MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for ICC measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period 64ms. (32ms for Military grade) This equates to an average refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; (35s for Military grade) burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: DQSL with DQ0-DQ7; and DQSH with DQ8-
FIGURE A - FULL DRIVE PULL-DOWN CHARACTERISTICS
160 140
FIGURE B - FULL DRIVE PULL-UP CHARACTERISTICS
0 -20 -40
Maximum
Minimum Nominal low
120
Nominal high
100
-60 -80 -100 -120 -140 -160
IOUT (mA)
80
Nominal low
60
IOUT (mA)
Nominal high
Minimum
40
20
-180
Maximum
0 0.0 0.5 1.0 1.5 2.0 2.5
-200 0.0 0.5 1.0 1.5 2.0 2.5
VOUT (V)
VCCQ - VOUT (V)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 18 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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DQ15 of each chip. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CK and CK# input slew rate must be 1V/ns (2V/ns differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VCC must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. The average cannot be below the 2.5V minimum. 37. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
W3E232M16S-XSTX
PRELIMINARY*
current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. 38. Reduced Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure C. b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure D. d) The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D. e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 V. 39. The voltage levels used are derived from a minimum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. 41. VCC and VCCQ must track each other. 42. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 43. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. 45. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW.47.Random addressing changing: 50% of data changing at every transfer. 48. Random addressing changing: 100% of data changing at every transfer.
FIGURE C - REDUCED DRIVE PULL-DOWN CHARACTERISTICS
80
FIGURE D - REDUCED DRIVE PULL-UP CHARACTERISTICS
0 -10 -20
Maximum
70
60
Nominal high
Minimum
50
-30
Nominal low
IOUT (mA)
IOUT (mA)
40
Nominal low
-40
30
-50
Minimum
20
-60
Nominal high
10
-70
Maximum
0 0.0 0.5 1.0 1.5 2.0 2.5
-80 0.0 0.5 1.0 1.5 2.0 2.5
VOUT (V)
VCCQ - VOUT (V)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 19 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
49. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. 50. ICC2N specifies the DQ, DQS, and DQM to be driven to a valid high or low logic level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is "worst case." 51. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ command. 52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC coltage range of 2.6V 100mV. 53. One TSOP current mode, one TSOP in precharge power down standby mode (IDD2P). 54. Both TSOPs in same current mode.
W3E232M16S-XSTX
PRELIMINARY*
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 20 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION
W3E232M16S-XSTX
PRELIMINARY*
W 3E 232M 16 S - XXX ST X X
WHITE ELECTRONIC DESIGNS CORP. DDR SDRAM CONFIGURATION, 2x32M x 16 2.5V Power Supply DATA RATE (MHz) 200 = DDR200 250 = DDR266 266 = DDR333 400 = DDR400 PACKAGE: ST = Stacked TSOP DEVICE GRADE: I = Industrial C = Commercial
-40C to +85C 0C to +70C
RoHS Compliance Blank = Not RoHS compliant G = RoHS compliant
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 21 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
64Mx16bit DDR SDRAM
W3E232M16S-XSTX
PRELIMINARY*
Revision History Rev #
Rev 0 Rev 1
History
Initial Release Change (All pages) 1.1 Add AC and DC electrical data 1.2 Add Product description and functionality 1.3 Add revision page 1.4 Change status to Preliminary
Release Date
February 2005 December 2005 Advanced Preliminary
White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 22 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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